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Separation Logic for High-level Synthesis
Title statement Separation Logic for High-level Synthesis [electronic resource] / by Felix Winterstein. Publication Cham : Springer International Publishing : Imprint: Springer, 2017. Phys.des. XIX, 132 p. 19 illus., 7 illus. in color. online resource. ISBN 9783319532226 Edition Springer Theses, Recognizing Outstanding Ph.D. Research, ISSN 2190-5053 Contents 1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices. Notes to Availability Přístup pouze pro oprávněné uživatele Another responsib. SpringerLink (Online service) Subj. Headings Engineering. * Computer memory systems. * Logic design. * Programming languages (Electronic computers). * Electronic circuits. Form, Genre elektronické knihy electronic books Country Německo Language angličtina Document kind Electronic books URL Plný text pro studenty a zaměstnance UPOL book
This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial ‘state of the art’. Implementing computation on customised digital hardware plays an increasingly important role in the quest for energy-efficient high-performance computing. Field-programmable gate arrays (FPGAs) gain efficiency by encoding the computing task into the chip’s physical circuitry and are gaining rapidly increasing importance in the processor market, especially after recent announcements of large-scale deployments in the data centre. This is driving, more than ever, the demand for higher design entry abstraction levels, such as the automatic circuit synthesis from high-level languages (high-level synthesis). The techniques in this book apply formal reasoning to high-level synthesis in the context of demonstrably practical applications.<.
1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices.
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